The present invention generally relates to microelectronic devices. More particularly, the present invention relates to bus drivers and receivers with improved signal integrity.
In digital systems, data is typically represented by a group of bits representing the value of that data, where the bit value is typically a logical high or a logical low. A logical high level is typically represented by a high-voltage level, such as that of the positive power supply, and a logical low level is typically represented by a low-voltage level, such as that of the device ground.
The processing of digital data typically involves transmitting signals representing individual bits from one digital block or subsystem to another digital block or subsystem. Since the representation of data contains of multiple bits (such as 8-bit words or 16-bit words), a digital bus typically transmits a parallel set of bits from one physical location to another using multiple traces.
In a typical digital system, the timing of the system may be critical. The signals are typically configured to recognize transitions between logical levels only at particular times. In addition, the voltage levels of the system may also be critical. For example, if 0 volts represents a logical low signal and 3.3 volts represents a logical high signal, a voltage level outside of predetermined voltage tolerances is ambiguous (e.g., it may not be possible to determine whether a voltage level of 1.6 volts represents a logical low or a logical high level.)
FIG. 1 illustrates a typical data bus where eight digital bits are transmitted from one location, represented by signals 101-108, to another location, represented by signals 111-118. The medium for transmission in FIG. 1 is an 8-bit bus having traces (121-128). In order to transmit the signal over the bus, drivers 131-138 are used to generate the proper signals to send via bus 121-128, and receivers 141-148 are used to detect the signal on the bus to generate the appropriate digital signals 111-118.
While the data bus has been described as taking the form of traces 121-128, the bus may take one of several different forms, such as traces on an integrated circuit, on a hybrid or package, a printed circuit board, a ribbon cable, or a backplane, depending on the location of the digital blocks or subsystems. Furthermore, the data bus may consist of a single destination and set of receivers or multiple destinations and sets of receivers.
Drivers 131-138 may include buffers (non-inverting) or inverters. Similarly, receivers 141-148 may consist of buffers or inverters, and digital signals 111-118, the respective outputs from receivers 141-148, may consist of an equivalent data representation of signals 101-108.
When a digital signal (representing the value of a single bit) switches from low to high, it may affect the signal on traces in physical proximity. Such spatial effects may include crosstalk, wherein the signal on one trace is coupled to the signal on another trace, or ground or supply bounce, wherein the voltage at ground and the power supply is not maintained at a relatively constant value due to the current flow used to effect the switching.
FIG. 2 illustrates a 2-dimensional cross-section of a typical 8-bit data bus. The data bus includes traces 201-208. The electrical characteristics of the bus depend on the physical dimensions of the traces (including the width, height, and spacing of the traces), the distance from the traces to a ground plane 209, and the characteristics of the dielectric material 210 which surrounds the traces. As noted above, the data bus may take various forms, such as traces on an integrated circuit, on a hybrid or package, a printed circuit board, a ribbon cable, or a backplane. However, for purposes of FIG. 2, they will be referred to as traces.
For typical chip and board interconnects, the electrical characteristics of the bus are dominated by the parasitic capacitance of the traces. Parasitic capacitance is the undesired capacitance that may result from the physical proximity of two electrical conductors. The parasitic capacitance may result from the proximity of a signal trace (201-208) to ground (209), as represented by parasitic capacitances 211-219, or from the proximity of one trace (201-208) to another trace (201-208), as represented by parasitic capacitances 221-227. There may also be additional parasitic capacitances due to other signal traces such as 231-233, represented by parasitic capacitances 234-237. For well-designed buses, however, the placement of traces 201-208 is often configured such that parasitic capacitances 231-233 are much less significant than the parasitic capacitance to ground (211-219) and the parasitic capacitance between traces (221-227).
FIG. 3 illustrates a three-dimensional view of a 3-bit bus with signal traces 301-303 and ground plane 304, similar to the 8-bit bus cross-section shown in FIG. 2. FIG. 3 illustrates that the length of the traces on a bus has an effect on the magnitude of the parasitic capacitances to ground and between traces, as the longer the traces are, the more area for which a capacitance to form. In general, the parasitic capacitances are proportional to the length of a trace, such that long buses have higher parasitic capacitance, but the relative ratio of those values are mostly dependent on the cross-sectional spacing.
Through the parasitic capacitance and inductance, the waveform on a signal trace will have an effect on adjacent traces; thus, the traces on the bus do not behave independently, but may be at least partially dependent on the signal waveforms on all traces. More particularly, a change in voltage or current in a trace can affect an adjacent trace through the parasitic capacitance and mutual inductance coupling. For simplification, the dominant terms for each trace can be considered for most practical cases to be the parasitic capacitance to ground and the parasitic capacitances to immediately adjacent traces, and the bus can be thought of consisting of a multiple port network or spatial filter.
The coupling results in undesirable deviations, such as crosstalk, to the waveform at the receiver such that the maximum operating frequency of the signals is typically limited for successful transmission and reception over the bus. Operating frequencies faster than the maximum operating frequency may result in difficulty in determining the proper state (logical high or logical low) of the various bits.
In addition, the current drawn by the buffers during signal transitions will vary depending on the number of signals transitioning simultaneously in the same direction, such as from logical-low to logical-high. This change in current leads to a variation in the voltage supply or the ground, resulting in a change in the signal waveforms, known as ground bounce.
When several devices are nearly simultaneously (i.e., during the same computing clock period) transitioning from a logical-low to a logical-high, and several other devices are also transitioning from a logical-high to a logical-low, the ground bounce presented is minimal, as the opposite switching directions of the devices may tend to cancel each other out, whereas when most signals transition in the same direction, the ground bounce is greater. Furthermore, when adjacent signals switch in opposite directions, coupling due to crosstalk is increased, resulting in smaller amplitudes and degraded transition times, making it more difficult to determine the correct state for each particular signal.
With reference to FIG. 8, several exemplary waveforms showing the possible effect of crosstalk and ground bounce are presented. In FIG. 8, an 8-bit bus (such as the one illustrated in FIG. 1) is modeled as a multiple-port network. The supply voltage and ground are modeled as series resistance and inductance in order to account for ground bounce.
The input waveform 801 is applied to input ports 101, 102, 103, and 105, while the logical inverse of input waveform 801 is applied to input ports 104, 106, and 107. Waveform 802 illustrates the signal on trace 122, while waveform 803 corresponds to the signal on trace 125. Ideally, trace 122 and 125 have the same logical values and transition nearly simultaneously. However, in the illustrated examples, the traces adjacent to trace 122 (i.e., trace 121 and trace 123) transition in the same direction. In contrast, the traces adjacent to trace 125 (i.e., trace 124 and trace 126) transition in the opposite direction because of the logical inverse signal at inputs ports 104 and 106. Thus, the result is that the signal represented by waveform 803 lags in time behind that of waveform 802.
Waveform 804 illustrates the output signal from receiver 112 and waveform 805 illustrates the output signal from receiver 115. As above, the signal represented by waveform 805 lags behind that of waveform 804. Such a time difference between the signals may result in timing failures. A timing failure may occur if the transition between a logical high level and a logical low level (or vice versa) occurs too late for a digital device to recognize the change, thus leading to an incorrect value.
Waveforms 806 and 807 depict the voltages at the power supply and the device ground. It can be seen that, instead of having a relatively constant value, the voltages fluctuate, which can result in logic failure due to either insufficient amplitude or timing margin if such fluctuations become too large.
Typical techniques for improving the maximum operating frequency include increasing the drive and amplitude of the buffers and slowing down the transition times to reduce the effects of crosstalk and ground bounce, but these provide only limited mitigation of the signal degradation. In state-of-the-art devices, as clock frequencies increase, device geometries decrease, and voltage supplies decrease, this problem becomes increasingly significant. More particularly, as clock frequencies increase, there is less time available to discern the correct value of each bit. A reduced device geometry (e.g., a 0.13 micron device in lieu of 0.25 micron device) places the various components and trace lines closer, possibly exacerbating the crosstalk problems described above. A reduced voltage supply (e.g., a 1.5 volt supply in lieu of a 5.0 volt supply), reduces the difference between signals with a logical high level and signals with a logical low level, possibly increasing the difficulty in discerning the correct value of each bit.
Accordingly, improved method and apparatus for reducing crosstalk and ground bounce within a data bus are desired.
The present invention is directed to a method and system for alleviating the above-described problems. A method in accordance with one embodiment of the present invention includes transmitting the data over the digital data bus using a spatially-filtered driver for each bit being transmitted such that the spatial effects of the digital data bus are countered. In accordance with an alternative embodiment, a method of transmitting signals employs the use of a spatially-filtered receiver for each bit such that the spatial effects of the digital data bus are countered. In accordance with another alternative embodiment, a method of transmitting signals may combine the use of a spatially-filtered driver and a spatially-filtered receiver for transmitting each bit.
A system of drivers in accordance with the present invention includes a first driver and a second driver. Both drivers are coupled to a positive power supply through a current-limiting device. Both drivers are also coupled to a ground though a second current-limiting device. The first current-limiting device is operable for a first type of transition while the second current-limiting device is operable for a second type of transition.
A system of receivers in accordance with the present invention includes a first receiver and a second receiver. A first current-limiting device is coupled to a voltage supply and to the first receiver. A second current-limiting device is coupled to the first receiver and to a ground. A third current-limiting device is coupled to a voltage supply and to both the first receiver and the second receiver. A fourth current-limiting device is coupled to a ground and to both the first receiver and the second receiver. A first capacitor may coupled the first and second receiver. This first capacitor may also be coupled to a power supply. A second capacitor may coupled the first and second receiver. This second capacitor may also be coupled to a ground. The first and third current-limiting devices are operable for a first type of transition while the second and fourth current-limiting devices are operable for a second type of transition.
An alternative driver system of the present invention includes a first and second driver. A first current-limiting device is coupled to a voltage supply and to the first driver. A second current-limiting device is coupled to a ground and to the first driver. A third current-limiting device is coupled to a voltage supply and to both the first driver and the second driver. A fourth current-limiting device is coupled to a ground and to both the first driver and the second driver.